JEDEC Solid State Technology Association, the global leader in standards development for the microelectronics industry, today announced publication of the JESD79-5A DDR5 SDRAM standard. This update to the JEDEC DDR5 SDRAM standard includes features designed to enhance reliability and performance in a wide range of applications involving client systems and high-performance servers. JESD79-5A is now available for download from the JEDEC website.
Added features designed to meet industry demand for improved system reliability include bounded fault error-correction support, Soft Post-Package Repair (sPPR) undo and lock, Memory Built-In Self-Test Post Package Repair (MBIST and mPPR), Adaptive RFM, and an MR4 extension. JESD79-5A expands the timing definition and transfer speed of DDR5 up to 6400 MT/s for DRAM core timings and 5600 MT/s for IO AC timings to enable the industry to build an ecosystem up to 5600 MT/s. The nomenclature for core timing parameters and their respective definitions has been revamped to closely align with the upcoming JEDEC JESD400-5 DDR5 Serial Presence Detect (SPD) Contents V1.0 standard. The document can be accessed here.
